Message boards : Questions and problems : Intel Xeon Phi Coprocessor
Message board moderation
Author | Message |
---|---|
Send message Joined: 7 Jun 16 Posts: 1 ![]() |
Will Boinc be using the Xeon Phi for any of its projects? They are going down in price. |
Send message Joined: 12 Feb 11 Posts: 420 ![]() |
Will Boinc be using the Xeon Phi for any of its projects? They are going down in price. Phi supports OpenCl, but i don't know if there are projects that support this hw. P.S. Where is the "down price"?? |
![]() Send message Joined: 13 Aug 15 Posts: 63 |
Someone else interested in xeon phis: https://boincstats.com/en/forum/15/10889,1 |
![]() Send message Joined: 23 Feb 12 Posts: 198 ![]() |
Xeon Phi's had been looked at over at GPUGrid according to a PM I had gotten. But they said they weren't efficient enough at that time. No idea if newer generation cards have changed things in that area. Other projects I had asked gave the typical: 1. Not enough of them out there to justify coding for it. 2. Not enough resources to get one/code one. 3. Not taking donations including hardware to code for one. Like GPU's, this topic seems to pop up every so many months. What we need is for someone to actually do the leg work at various projects themselves and present their findings to the admins. ![]() |
Send message Joined: 12 Feb 11 Posts: 420 ![]() |
New Xeon Phi seems to be x86 compliant and permits OS boot, like a normal cpu. So 72 core Atom for boinc :-O |
Send message Joined: 24 Aug 15 Posts: 16 ![]() |
New Xeon Phi seems to be x86 compliant and permits OS boot, like a normal cpu. Yes, I would think there wouldn't be issues running cpu threads on these as they are x86. They're atom derived cores, but kind of like atom cores on steroids. From what I've read they have two FPU/MMX units per core and two ALUs and are very good at float; they are highly SMT/hyperthreading and run 4 threads per core. Loading a core with 4 threads will slow down per thread speed but massively speed up rate of total work done and efficiency. Like the atom they are in-order instruction CPUs; speed is sacrificed for power efficiency. Especially in an high thread scenario, hardly anything will beat these in efficiency (although some of the more efficient risc and arms i would guess, might). The total of 288 threads is spectacular but these are anything but cheap. Even if the price goes down they still will cost about $100 per core. We are talking ballpark prices $5k-$10k for phi units.) An FX6300 ($100/CPU) or Athlon X4 845 costs just $17 per core and are high performance out of order CPUs; the latter being fast and very efficient if you clock around 2.4GHz-3.1GHz. The Old FX6000 or 8000s piledriver cores are decenty efficient if you clock down under 2.5GHz (laptop speeds). On the Athlon X4 you can run 2 or 3 threads while computing and using the desktop; so I'm quite happy with that one as a BOINC puter. AMD Zen chips will be 8c/16t probably with very good $/perf if Polaris prices are any gauge; I hope to try one this coming winter. |
Send message Joined: 6 Jul 10 Posts: 585 ![]() |
288 Threads, and current BOINC limited to 200 job slots IIRC... which can be overcome by setting to allow multiple clients. Coelum Non Animum Mutant, Qui Trans Mare Currunt |
Send message Joined: 24 Aug 15 Posts: 16 ![]() |
288 Threads, and current BOINC limited to 200 job slots IIRC... which can be overcome by setting to allow multiple clients. Interesting bit of info. Having most of the cores HT 3 rather than 4 threads might not impact perf too dramatically if scheduler does a good job at maximizing business of execution units. Would be an interesting test though. The slightly inferior 64 thread version has a very nice discount; it s only a bit over $2400. http://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%207210.html I was mistaken about these atoms being in-order; since silvermont (22nm gen) atoms have been upgraded to out-of-order execution for better single thread perf. (When loaded with max logical threads i m guessing maybe the scheduler will avoid reordering unless it s trivial.) http://www.realworldtech.com/silvermont/ https://en.wikipedia.org/wiki/Silvermont I imagine that these slow but massive thread capable chips will do great on tasks where memory performance is the major bottleneck and where cache misses are the usual case. |
Copyright © 2025 University of California.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License,
Version 1.2 or any later version published by the Free Software Foundation.